The present invention generally relates to a switching control method for DC/DC converters.
DC/DC converters are used in many applications but are especially important in portable electronic devices such as cellular phones, tablets and laptop computers which are supplied with power from batteries primarily. A DC/DC converter conventionally uses switching of a DC input voltage to produce a lower DC output voltage to drive its load, and uses a feedback loop to adjust the switching parameters in order to keep the output voltage in a region around a selected average voltage. A common conventional DC/DC converter uses a sawtooth waveform and comparator for pulse width modulation (PWM) in the feedback loop to control the average voltage by keeping the frequency of the pulses constant while adjusting the pulse width. This type of DC/DC converter however is not generally chosen for low-load converters due to poor efficiency at low loads and since other, simpler designs are available. One such simpler design approach is the Constant On-Time (COT) DC/DC converter which uses a single-shot fixed pulse width pulse generator and a variable pulse frequency to adjust the feedback loop. Another design suitable for low-load applications is the dual threshold hysteretic converter which uses comparison of the output voltage against dual reference voltage thresholds. However, both the COT type and dual threshold type DC/DC converter, while versatile for low load applications can have stability problems requiring conventional complex compensation techniques.
Using the conventional low load COT-type DC/DC converter as an example, operation and stability is discussed below.
FIG. 1 illustrates a DC/DC converter 100 which is a conventional Constant On-Time (COT) hysteretic low load DC/DC converter using one-shot pulse generation.
As shown in the figure, DC/DC converter 100 includes a filter 101, a ground plane 106, a VOUT node 108, a load 110, a resistor ladder 112, an adder 114, an adder input 116, an Emulated Ripple Generator (ERG) 120, a hysteretic comparator 122, a reference voltage 126, a one-shot pulse generator/driver 130, a switch 132, a VIN node 134 and a diode 136. Filter 101 includes an inductor 102 and a capacitor 104. Hysteretic comparator 122 has a comparator input 124 and a comparator input 128.
Inductor 102 is arranged between switch 132 and capacitor 104. Capacitor 104 is arranged to connect between ground plane 106 and inductor 102. Load 110 is arranged to connect between capacitor 104 and ground plane 106. VOUT node 108 is arranged to be the shared connection of inductor 102, capacitor 104, load 110 and resistor ladder 112. Switch 132 is arranged between VIN node 134 and the shared connection of diode 136 and inductor 102. Diode 136 is arranged between switch 132 and ground plane 106. Output ripple voltage 116 is arranged to be the shared connection of resistor ladder 112 and adder 114. ERG 120 is arranged to connect to adder 114. An emulated ripple voltage 118 is arranged to be the shared connection of ERG 120 and adder 114. Adder 114 is arranged to connect to hysteretic comparator 122 at comparator input 124. Reference voltage 126 is arranged to connect to hysteretic comparator 122 at comparator input 128. Hysteretic comparator 122 is arranged to connect to one-shot pulse generator/driver 130. One shot pulse generator/driver 130 is arranged to connect to switch 132.
VIN node 134 receives input voltage VIN and provides current through inductor 102 to charge capacitor 104, when switch 132 is on. Capacitor 104 charges through inductor 102 to provide output voltage 108 and output current through load 110. Diode 136 prevents discharge of capacitor 104 through inductor 102. Resistor ladder 112 provides ripple voltage 116, a derivation of an output voltage, VOUT, at VOUT node 108, to comparator 122 via adder 114. ERG 120 provides emulated ripple voltage 118. Adder 114 adds ripple voltage 116 and emulated ripple voltage 118 and provides the sum to hysteretic comparator 122 at comparator input 124. Reference voltage source 126 provides a reference voltage for comparison by hysteretic comparator 122 at comparator input 128. Reference voltage 126 sets the average output voltage of DC/DC converter 100. Hysteretic comparator 122 provides, with some finite hysteresis, an output to one-shot pulse generator/driver which is generally low when the voltage at comparator input 124 is greater than the voltage at comparator input 128 and high when the voltage at comparator input 124 is less or equal to the voltage at comparator input 128. One-shot pulse generator/driver produces a pulse of fixed duration whenever hysteretic comparator 122 goes high. One-shot pulse generator/driver also drives switch 132 ON during the pulse and OFF when the pulse is absent.
In operation, the DC/DC converter converts VIN to a lower VOUT, driving a load RL. This will be described with additional reference to FIG. 2.
FIG. 2 illustrates the timing diagram 200 showing the behavior of various parameters of DC/DC converter 100 over time.
As shown in the figure, timing diagram 200 includes a switch waveform 202, an X-axis 204, a Y-axis 206, a time t1 illustrated by dotted line 208, a time t2 illustrated by dotted line 210, a time t3 illustrated by dotted line 212, a current waveform 214, an X-axis 216, a Y-axis 218, a voltage waveform 220, an X-axis 222, and a Y-axis 224.
X-axis 204, X-axis 216 and X-axis 222 represent time. Referring also to FIG. 1, Y-axis 206 represents the voltage at the output of switch 132. Y-axis 218 represents the current through inductor 102 and Y-axis 224 represents VOUT at VOUT node 108.
The case where emulated ripple voltage 118 is zero will be initially considered starting with condition where switch 132 has just turned on.
Switch 132 has been turned on by the pulse from one-shot pulse generator/driver 130. Waveform 202 of FIG. 2 shows this at time t1, (dotted line 208). This allows VIN to charge capacitor 104 through inductor 102 and iL rises (waveform 214) as does VOUT (waveform 220).
After the fixed ON-time, tON, (see waveform 202) the pulse generated by pulse generator/driver 130 expires at time t2 (dotted line 210) and switch 132 goes off. With switch 132 off, waveform 214 shows that current through inductor 102 ramps down as capacitor 104 discharges through load 110. Note that diode 136 prevents discharge of the capacitor through inductor 102. As capacitor 104 discharges, VOUT also falls as shown by waveform 220.
After some time, VOUT falls sufficiently that voltage ripple 116 falls below the value of VREF at comparator input 128 and comparator 122 changes states, triggering a pulse from one shot pulse generator/driver 130. This is now the start of a new cycle.
VOUT at VOUT node 108 appears as voltage ripple VRIPPLE at load 110 about a nominal DC voltage VDC.
The behavior described above illustrates that output voltage regulation of a COT DC/DC converter with zero emulated ripple is achieved by comparing VOUT to VREF. Under certain conditions and without additional circuitry, COT DC/DC converters can enter states where they become unstable such that a consistent output from cycle to cycle within the desired voltage range cannot be maintained.
In addition, VRIPPLE must be large enough to overcome the comparator hysteresis in order for the comparator to change states. Accordingly, since the output ripple is directly proportional to the ESR of the output capacitor, it follows that the ESR must also be large enough for VRIPPLE to toggle the comparator properly and consistently. Ceramic capacitors have significant advantages in cost, reliability, stability, and circuit space over bulk electrolytic capacitors and as such it is very desirable to use them in low load DC/DC converters. However, when used in such circuits as described above, the very low ESR of ceramic capacitors and resulting low ripple levels in circuits such as those described above can cause the switching and therefore the operation of the converter to become unstable.
A conventional remedy for the instabilities discussed above is to inject a controlled amount of additional ripple at the comparator input using an emulated ripple generator. The ERG ripple is controlled so that the regulation is predictable over all cycles. Referring to FIG. 1, ERG 120 provides this additional ripple, introducing it to the comparator via adder 114. Use of an ERG, however introduces additional DC error at the converter output and so further measures, conventionally high gain amplifiers, are needed to reduce these.
A conventional COT DC/DC convener described above can operate in Continuous Conduction Mode (CCM), a mode whereby the current through the inductor is always positive. A system operating in CCM is a second-order system, that is, the transfer function describing the system is a second order function. A converter can also be designed to operate in Discontinuous Conduction mode (DCM) characterized by the inductor current falling to zero for a period of time. A converter operating in DCM is a first order system, which is an inherently more stable system.
CCM and DCM operation can also be illustrated with a diagram.
FIG. 3 shows timing diagram 300 which illustrates the modes of operation CCM and DCM.
Timing diagram 300 shows the switching and inductor current waveforms from timing diagram 200 which represent CCM operation, but adds an additional inductor current waveform to illustrate DCM operation.
As shown in the figure, timing diagram 300 includes switch waveform 202, X-axis 204, Y-axis 206, time t1 illustrated by dotted line 208, time t2 illustrated by dotted line 210, time t3 illustrated by dotted line 212, current waveform 214, X-axis 216, Y-axis 218, a current waveform 302, an X-axis 304, and a Y-axis 306.
X-axis 204, X-axis 216 and X-axis 304 represent time. Referring also to FIG. 1, Y-axis 206 represents the voltage at the output of switch 132 and Y-axis 218 represents the current through inductor 102 for the CCM case. Y-axis 306 represents the current through inductor 102 for the CCM/DCM case.
The operation of DC/DC converter 100 has been explained previously and is not covered again in this description.
In the figure, current waveform 214 shows the behavior over time of the current through inductor 102, iL. Current waveform 214 shows iL for the case where the load is sufficiently high to ensure that operation stays in CCM. This is indicated, by iL staying above zero for current waveform 214.
Current waveform 302 shows iL for the case where the load is sufficiently reduced such that operation enters DCM for a portion of the cycle. This is indicated in current waveform 302 by the portions of the cycle for which iL has reached zero. As explained previously, a converter operating in DCM is an inherently more stable system.
Stabilization compensation techniques, such as ERG as described above and used for conventional converters such as COT converters operating in CCM, can substantially increase the design complexity of low load DC/DC converter design. This added complexity can significantly impact design time, circuit area, gate count and therefore cost and size, two qualities which are essential for portable electronics production.
What is needed is a simpler low load DC/DC converter design that mitigates the stability issues described above but that does not require the additional circuitry needed to implement conventional stabilization techniques such as ERG or the additional circuitry then needed to reduce the DC errors caused by the stabilization technique.